? semiconductor components industries, llc, 2010 april, 2010 ? rev. 1 1 publication order number: NYC0102BL/d NYC0102BLt1g sensitive gate silicon controlled rectifiers reverse blocking thyristors designed and tested for highly ? sensitive triggering in low-power switching applications. features ? high dv/dt ? gating current < 200 a ? miniature sot ? 23 package for high density pcb ? this is a halogen ? free device ? this is a pb ? free device maximum ratings (t j = 25 c unless otherwise noted) rating symbol value unit peak repetitive off ? state voltage (note 1) (r gk = ik, t j = 40 to +110 c, sine wave, 50 to 60 hz v drm, v rrm 200 v on-state current rms (180 conduction angle, t c = 80 c) i t(rms) 0.25 a peak non-repetitive surge current, t a = 25 c, (1/2 cycle, sine wave, 60 hz) i tsm 7.0 a circuit fusing considerations (t = 8.3 ms) i 2 t 0.2 a 2 s forward peak gate power (pulse width 1.0 sec, t a = 25 c) p gm 0.1 w forward average gate power (t = 8.3 msec, t a = 25 c) p g(av) 0.02 w forward peak gate current (pulse width 20 s, t a = 25 c) i fgm 0.5 a reverse peak gate voltage (pulse width 1.0 s, t a = 25 c) v rgm 8.0 v operating junction temperature range @ rated v rrm and v drm t j ? 40 to +125 c storage temperature range t stg ? 40 to +150 c thermal characteristics characteristic symbol max unit total device dissipation fr ? 5 board t a = 25 c p d 225 mw thermal resistance, junction ? to ? ambient r ja 380 c/w stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. 1. v drm and v rrm for all types can be applied on a continuous basis. ratings apply for zero or negative gate voltage; however, positive gate voltage shall not be applied concurrent with negative potential on the anode. blocking voltages shall not be tested with a constant current source such that the voltage ratings of the devices are exceeded. 0.25 amp, 200 volt scrs pin assignment 1 2 3 gate anode cathode k g a http://onsemi.com sot ? 23 case 318 style 8 marking diagram 1 2 3 1 c2b m c2b = specific device code m = date code* = pb ? free package (note: microdot may be in either location) *date code orientation and/or overbar may vary de- pending upon manufacturing location. device package shipping ? ordering information NYC0102BLt1g sot ? 23 (pb ? free) 3000/tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d.
NYC0102BLt1g http://onsemi.com 2 electrical characteristics (t c = 25 c unless otherwise noted.) characteristic symbol min typ max unit off characteristics peak repetitive forward blocking current (v drm = 200 v, r gk = 1 k )t c = 25 c t c = 125 c i drm ? ? ? ? 1.0 100 a a peak repetitive reverse blocking current (v drm = 200 v, r gk = 1 k )t c = 25 c t c = 125 c i rrm ? ? ? ? 1.0 100 a a on characteristics peak forward on ? state voltage (i tm = 0.4 a, t p < 1 ms, t c = 25 c) v tm ? ? 1.7 v gate trigger current (v d = 12 v, r l = 100 , t c = 25 c) i gt ? ? 200 a gate trigger voltage (v d = 12 v, r l = 100 , t c = 25 c) v gt ? ? 0.8 v holding current (i t = 50 ma, r gk = 1 k , t c = 25 c) i h ? ? 6.0 ma gate non ? trigger voltage (v d = v drm , r l = 3.3 k , t c = 125 c) v gd 0.1 ? ? v latching current (i g = 1.0 ma, r gk = 1 k , t c = 25 c) i l ? ? 7.0 ma gate reverse voltage (i rg = 10 a) v rg 8.0 ? ? v dynamic characteristics critical rate of rise of off ? state voltage (r gk = 1 k , t c = 125 c) dv/dt 200 ? ? v/ s critical rate of rise of on ? state current (i g = 2xi gt 60 hz, t r < 100 ns, t j = 125 c) di/dt ? ? 50 a/ s + current + voltage v tm i drm at v drm i h symbol parameter v drm peak repetitive off state forward voltage i drm peak forward blocking current v rrm peak repetitive off state reverse voltage i rrm peak reverse blocking current v tm peak on state voltage i h holding current voltage current characteristic of scr anode + on state reverse blocking region (off state) reverse avalanche region anode ? forward blocking region i rrm at v rrm (off state)
NYC0102BLt1g http://onsemi.com 3 i t , average current (a) figure 1. maximum average power vs. average current figure 2. current derating 0 0.05 0.1 0.15 0.2 0.25 0.3 0 50 100 150 t, temperature ( c) i t , average current (a) dc 180 figure 3. surge current itsm vs. number of cycles 0 3 7 1 10 100 1000 number of cycles itsm (a) figure 4. thermal response pulse duration (s) transient resistance (normalized) figure 5. on ? state characteristics v tm , (v) i tm , (a) figure 6. gate trigger current vs. t j (normalized to 25 c) t j , (k) p, average power (w) 0 0.05 0.1 0.15 0.2 0.25 0 0.05 0.1 0.15 0.2 4 5 6 2 1 0 0.2 0.4 0.6 0.8 1 1.e ? 04 1.e ? 03 1.e ? 02 1.e ? 01 1.e+00 1.e+01 1.e+02 1.e+03 0.1 1 10 0 0.5 1 1.5 2 2.5 25 c 125 c 0 0.5 1 1.5 2 200 250 300 350 400 gate open r gk = 1k
NYC0102BLt1g http://onsemi.com 4 0 0.5 1 1.5 2 200 250 300 350 400 figure 7. gate trigger current vs. t j (normalized to 25 c) t j , (k) gate open r gk = 1k 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 024681012 figure 8. gate trigger current vs. r gk i gt (ma) r gk , (k ) 0 5.0 10 15 25 0246810 1 i h ,i l (ma) figure 9. holding and latching current vs. r gk r gk , (k ) 0 500 1000 1500 2000 024681012 figure 10. dv/dt vs. r gk r gk , (k ) dv/dt (v/ s) 20 3579 0 0.20 0.40 0.60 0.80 1.0 200 250 300 350 400 v gt (v) figure 11. gate triggering voltage vs. t j t j , (k)
NYC0102BLt1g http://onsemi.com 5 package dimensions mm inches scale 10:1 0.8 0.031 0.9 0.035 0.95 0.037 0.95 0.037 2.0 0.079 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* sot ? 23 (to ? 236)] case 318 ? 08 issue an style 8: pin 1. anode 2. no connection 3. cathode d a1 3 12 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. maximum lead thickness includes lead finish thickness. minimum lead thickness is the minimum thickness of base material. 4. 318 ? 01 thru ? 07 and ? 09 obsolete, new standard 318 ? 08. view c l 0.25 l1 e e e b a see view c dim a min nom max min millimeters 0.89 1.00 1.11 0.035 inches a1 0.01 0.06 0.10 0.001 b 0.37 0.44 0.50 0.015 c 0.09 0.13 0.18 0.003 d 2.80 2.90 3.04 0.110 e 1.20 1.30 1.40 0.047 e 1.78 1.90 2.04 0.070 l 0.10 0.20 0.30 0.004 0.040 0.044 0.002 0.004 0.018 0.020 0.005 0.007 0.114 0.120 0.051 0.055 0.075 0.081 0.008 0.012 nom max l1 h 2.10 2.40 2.64 0.083 0.094 0.104 h e 0.35 0.54 0.69 0.014 0.021 0.029 c on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 NYC0102BL/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
|
